Wrapper Tool
Principles of Design for Testability techniques
and
generation of wrapper structure applications
|
| * Introduction |
This software tool automatically generates and synthetises wrapper architectures for testability of digital circuits/cores. A learning module for explaining principles of these testability technique features applicated to a circuits/cores is a part of the tool. |
| * Method |
The
tool deals with IEEE P1500 Embedded-core Test Standard
(wrapper), which were developed and recommended by IEEE as DfT standard
for testable SoC design. |
| * Tool description |
The tool consists of three modules:
- module for demonstration of the wrapper architecture,
- module for the wrapper structure generation,
Tool input: the VHDL entity of a circuit, tool output: the VHDL code of the whole wrapper architecture applied to the core. |
| * Example |
under
construction |
| * Requirements |
Web browser with Sun Java plug-in (1.3 or higher) installed. |
| |
Select a module to start the applet :
|
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Wrapper Generator ©2002 - 2004 Institute of Informatics SAS
Contact: Marcel Baláž, marcel.balaz@savba.sk |
