Tools Wrapper BIST MemBIST  


Testability

of digital circuits and systems
 
* Introduction Diagnosis and testability are inevitable parts of every electronic system design. "A digital IC is testable if test patterns can be generated, applicated, and evaluated in such a way as to satisfy pre-defined levels of preformance (e.g. detection, localisation, application) within a pre-defined cost budget and time scale." (R.G. Bennetts, Design of Testable Logic Circuits, Addison-Wesley, 1984).
* Methods

Design methods developed to improve the testability of designed circuits/systems are:

  1. design for testability (DfT)
    - heuristics (ad hoc methods) - including test points into the circuit (it requires very good design knowledge and skills);
    - structure or "scan" methods - can be divided into external and internal. These are also the IEEE standards 1149.1 "Test Test Access Port and Boundary-Scan Architecture" and P1500 "Embedded-core Test".
  2. built-in self-test (BIST) for logic and memory circuits
    The aim of these methods is a hardware realisation of a built-in test generator and of a test result evaluation. The advantages of BIST are at-speed testing and low testing cost.
* Web-based tools

Some DfT standards and BIST techniques are parts of professional CAD tools (e.g. Mentor Graphics, Synopsis).
The offered products - BIST applet, MemBIST applet and Wrapper applet, developed at our research Institute, can help to gain knowledge and skills of known and often used DfT and BIST methods.

II SAS
 Web-based tools for testing (c) Institute of Informatics SAS
Contact: Elena Gramatová, elena.gramatova@savba.sk